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% LaTeX technical info: see "A Document Preparation System" 2nd
%   edition, Leslie Lamport
% author of this document: Peter Stallinga

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\begin{center}
  \fbox{\LARGE Project 2}\\
  {\tiny P.\ Stallinga, 23.05.2001}\\
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\end{center}

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\noindent
The circuit consists of the following elements:
\begin{description}
\item[I] \textbf{differential pair}. The entrance resistance is
  determined by the emittor resistances: $r_i = r_\pi+(\beta+1)R_E$.
  For a $\beta$ of 100 and the requirement of $r_i>10$ k$\Omega$ we
  have $R_E > 68$ $\Omega$ (assuming $r_e$ = 35 $\Omega$.\\
  The voltage gain of the difpar is given by $A_v = R_C/(r_e+R_E)$.
  With $R_C$ is 2.2 k$\Omega$ we get $A_v$ = 16. This value is not
  meaningful, because at the exit of the difpar the
  Common-Base (with low input resistance) is connected, see (III).\\
\item[IIa] \textbf{current source 1}. The value of the current is
  given by the requirement that the bias point of output of the difpar
  of (I) is about halfway between +Vcc (+15 V) and the base of Q2 (0
  V). For the difpar above, with $R_C$ = 2.2 k$\Omega$ a current of
  about 6.8 mA works well.
\item[III] \textbf{Common Base}. The input resistance of the common
  base is very low ($r_e$, because $R_B$ is bypassed). This loads and
  distorts the difpar whose gain is reduced to $(R_C\parallel
  r_e)/(r_e+R_E)$. The gain of the CB is given by $R_L/r_e$, so that
  the overall gain is
\begin{eqnarray}
 A_v = \frac{R_C\parallel r_e}{r_e+R_E} \cdot \frac{R_L}{r_e} \approx \frac{R_L}{r_e+R_E}
\end{eqnarray}
with $r_e$ and $R_E$ of the difpar and $R_L$ the load resistance of
the CB. For the load resistance of 27 k$\Omega$ we get therefore $A_v$
= 200. In reality it is much lower.  The resistances at the base
should be chosen in such a way that the transistor is open. At the
output of the difpar we had 7.5 V and the base of the CB should
therefore be below 6.8 V. The bypas capacitor makes the input
resistance of the CB very low.
\item[V + IIb] The load resistor combined with the second current
  source are to make the bias at the entrance of the last stage equal
  to zero, so that we have no DC current at the output of our
  amplifier. A variable resistor is a good idea for this load
  resistor.
\item[IV] The last part is a current amplifier driven by an
  opamp. This has no voltage
  amplification but can supply a large current needed for an 8
  $\Omega$ load at the output. This stage is symmetrical with each
  side taking care of half of a wave. Each side is comprised of a
  Darlington pair, which has a huge current amplification,
  $(\beta+1)^2$, but no voltage amplification. The output resitance of
  this stage is basically the emittor resistance: $R_E +
  R_B/(\beta+1)^2$, with $R_B$ the resistance at the base of the first
  transistor (k$\Omega$'s).\\
  The opamp 'regulates' the output of the amplifier such that the
  difference at the input of the opamp is nulled. We therefore need  a
  zero DC level at the input of the opamp. Hence the variable resistor
  (V).

\end{description}

\vspace{3cm}
\noindent
\emph{\small \textsc{Annex:}\\
Simulations with Electronic Workbench 5.12 and PSpice 8.0}
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